quapona technologies

Autoren: Jörn Hoffmann, Dirk Zeckzer, Martin Bogdan

We present a proof-of-concept implementation of Myers bit-vector algorithm for approximate string matching in hardware. In terms of bit-vector operations, the algorithm is accelerated by using the massive parallel computing capabilities of a field programmable gate array (FPGA). The system is realized on an embedded platform with a high computational efficiency and energy efficiency. Compared to the fastest software implementation running on the embedded processor, the hardware achieves an overall speed-up of approximately 2 and a speed-up of approximately 8 considering the computation only.

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