quapona technologies

Autoren: Jörn Hoffmann, Frank Güttler, Karim El-Laithy, Martin Bogdan

In this work a novel approach to automatically generate hardware is introduced that allows accelerated simulation of artificial neural networks (ANN) on field-programming gate arrays (FPGAs). A compiler architecture has been designed that primarily aims at reducing the development effort for non-hardware developers. This is done by implementing automatic generation of accordingly adjusted hardware processors. Deduced from high-level OpenCL source code, the processors are able to spatially map ANNs in a massive parallel fashion.

Quelle: ICANN 2012, LNCS 7552, p.169-176, 2012

Link: http://link.springer.com/chapter/10.1007%2F978-3-642-33269-2_22

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