In this work a novel approach to automatically generate hardware is introduced that allows accelerated simulation of artificial neural networks (ANN) on field-programming gate arrays (FPGAs). A compiler architecture has been designed that primarily aims at reducing the development effort for non-hardware developers. This is done by implementing automatic generation of accordingly adjusted hardware processors. Deduced from high-level OpenCL source code, the processors are able to spatially map ANNs in a massive parallel fashion.
Autoren: Jörn Hoffmann, Frank Güttler, and M. Bogdan
Quelle: DATE 2011, Grenoble, 2011